Vidicon camera tube and target

ABSTRACT

A vidicon camera tube having a semiconducting target whose one face contains an array of reverse biased charge storing junction diodes periodically scanned by a charging beam of electrons and whose opposite face is exposed to light from an image so as to discharge selected ones of the diodes. A conductive grid in the target below the level of the diodes provides improved operating characteristics.

[ May 13, 1975 United States Patent 1 nnila VIDICON CAMERA TUBE AND TARGET FOREIGN PATENTS OR APPLICATIONS 2.033.992 11/1970 313/66 1,221,896 2/1971 United Kingdom................... 313/66 [75] Inventor: Ronald M. Finnila, Costa Mesa,

Calif.

[73] Assignee: Hughes Aircraft Company, Culver City, Calif.

Primary Examiner-Robert Sega] Attorney, Agent, or FirmW. H. MacAllister; J. E. Szabo [22] Filed: Aug. 19, 1971 [21] Appl. No.: 173,207

charge storing junction diodes periodically scanned by a charging beam of electrons and whose opposite face discharge 78 63N B 33R MUN .03 m s ms MMB mmA U J H3 m 3 ac "Ur "mm 1 C w WM Umfi H 555 [[1 is exposed to light from an image so as to [561 g zffi gi selected ones of the diodes. A conductive grid in the target below the level of the diodes provides improved operating characteristics.

313/66 Hofstein 313/65 AB 3 Claims, 13 ng Figur s 3.0111189 11/1961 Reynolds........................ 3,517,246 6/1970 Chester et al.... 3 646 391 2/1972 PATENTED MAY 1 31975 SHEEI 2 BF 5 Fig.4.

T0 CATHODE HEM Y I 33375 SHEEI 30F 5 Fig.6.

US i

Q 1 7 Kb XXX Fig.5.

wwwwwww PXJEHIEDHM 1 3i975 2.883 769 SHEEI W 5 Fig. 70.

Fi Yb.

1 J I I/ l J l Fig.7c.

Fig.7d.

VIDICON CAMERA TUBE AND TARGET The present invention relates generally to image transducing devices of the type wherein the image is stored as a charge pattern in a semiconducting target element having an array of diodes in one of its faces which is swept by an electron beam. and more particularly to a vidicon camera tube using such a target element.

The target element of the above type is basically comprised of a wafer of semiconducting material doped to have an N-type conductivity, with one of the major faces of the wafer being selectively doped to have a large plurality of P conductivity type regions, respective ones of the regions forming a junction diode with the substrate thereunder. The substrate is maintained at a potential which is positive with respect to the scanning electron beam so that, as the P conductivity type regions are bombarded with electrons they become reverse biased. In the reverse biased state each of the junction diodes stores an electric charge, electrons, derived from the beam and maintains that charge at least until it is scanned again. The reverse bias maintained on the junction diodes in the target element and the charges stored in the diodes create a depletion re gion" in the substrate under each diode and also between adjacent diodes, these regions being characterized by a shortage of majority carriers (electrons in the case of an N conductivity type material) and by an electric field across the region.

The opposite face of the target element receives light from an image and photons thus striking the target cause electron-hole pairs to be generated in the substrate of the target. A substantial number of the holes thus generated reach the diodes opposite the point of photon impact, where they combine with and hence eliminate a corresponding number of stored electrons.

In particular, the holes thus generated migrate through the body of the target wafer until they reach the depletion region, where they are rapidly swept into the nearest diode by the electric field existing across the region. In this manner a charge pattern is created in the array of diodes, corresponding to the image striking the opposite face of the target element, with each diode having its stored charge diminished by an amount corresponding to the time integral of the light striking the corresponding spot on the light-receiving side of the target element. Consequently, upon its next scan, the electron beam charges each diode by an amount corresponding to the charge lost by that diode. The amount of charging current from the electron beam is detected by circuitry associated with the target and provides a signal representative of the detected image.

A vidicon camera tube using a diode target of the above type is described in Wendland U.S. Pat. No. 3,423,623 assigned to the assignee ofthe present invention. Although the junction diode target has been recognized as a significant advance in the vidicon art, it has several inherent limitations which it is the object of the present invention to minimize. One limitation ofthe junction diode target and of the tube utilizing it is that there tends to be a leakage current, also called dark current, tending to discharge the reverse biased charge storing diodes, even in the absence of light. Leakage current is caused by the flow of minority carriers (holes for an N-type substrate) from the substrate into the P conductivity type diode regions, where they recombine with, and hence eliminate electrons stored therein. Such leakage current is known to be caused by the generation of hole-electron pairs in the body of the target element at particular sites calleld generationrecombination centers" which tend to occur l where there is a defect or impurity in the semiconducting substrate, (2) where there is a transistion between differently doped areas in the material, and (3) where substrate interfaces with another material. Generationrecombination centers are particularly important when they are located within the depletion regions associated with the charge storing junction diodes because of the electric field which exists in those regions.

The presence of an electric field at a generationrecombination center tends to separate the electronhole pair so as to prevent the members of the pair from recombining with, and hence eliminating, one another. Consequently, when an electron-hole pair is created by a generation-recombination center located within the depletion region of a diode, the hole member of the pair is swept into the diode where it combines with a stored electron and effectively discharges the diode to that extent. Thus, the amount ofleakage current is proportional to the volume ofthe depletion region and also to the area of the target substrate surface between adjacent diodes, since the latter is an interface where generation-recombination centers tend to occur in relatively large numbers. Usually, the surface portions of the target material between adjacent diodes is covered with an insulator in order to prevent electrons from landing directly on the target material and generation recombination centers tend to occur at the interface of the insulating material and the semiconducting wafer substrate.

A second inherent limitation of the junction diode target is commonly referred to as blooming" and has been described in detail in a paper entitled Low Light Level Imaging In The Presence of High intensity Point Sources" by Steven B. Campana, the Proceedings of the Technical Program, Electro Optical Systems De sign Conference, New York City, Sept. 2224, 1970, Section 7, pp. 562-573. Blooming" occurs when the target is exposed to a relatively high intensity point source in a relatively low light level background. Under these conditions the number of holes generated as a result of the point light source is greater than the charge storing capacity of the corresponding diodes in the target. As a result, when less than all of the generated holes have discharged the diodes nearest the point of light impact, the remaining holes spread laterally through the target substrate and are swept into the nearest adjacent diodes, tending to discharge them also. This lateral spreading of holes thus has the tendency of discharging too many diodes and is manifested by a relatively large, circular, bright image whose size increases with the intensity of the point light source.

A third limitation inherent in the junction diode target is that it has a tendency to form an inversion layer in the substrate between adjacent diodes as a result of the impinging of electrons from the scanning beam upon the target wafer substrate. The electron beam imposes a negative potential on the surface of the wafer substrate relative to its body and if this negative potential is sufficiently large it will attract a sufficient number of holes to the wafer substrate surface to convert it into a P conductivity type layer. This P conductivity type layer effectively short circuits the P conductivity type regions of the adjacent diodes between which it is formed by the electron beam so that if one of those diodes is discharged as a result of incident light. it will also discharge the adjacent diode to which it is so short circuited.

The effect of field inversion in a target is to render the target inoperative. The solution is to limit the target potential (the bias voltage between the electron beam potential and that of the target substrate) to a sufficiently low level so that inversion will not occur. While in most applications this limitation is not of great consequence. since the permissible target potential is still sufficiently high to permit useful target operation, there are certain modes of target operation. such as the ava lanche" mode, which can only be obtained at target potentials which with presently existing targets would cause inversion to occur.

It is a principal object of the present invention to produce an improved vidicon camera tube, and in particular one whose low light intensity level operation is less affected by high intensity point light sources than are currently available tubes of this type. In this connection it is an object of the present invention to reduce blooming in junction diode vidicon targets.

A related object ofthe present invention is to provide an improved junction diode vidicon target and in particular one having a low susceptability to a high intensity point light source in a low intensity light background. as well as a lower inherent leakage current and a greater resistance to inversion than existing junction diode vidicon targets.

These and other objects of the invention are achieved by a vidicon camera tube having a charge storing target element of the junction diode type in which an array P conductivity type regions are disposed on one face of an N conductivity type semiconductive wafer substrate so as to form a plurality of P-N junctions therewith. Disposed in the wafer below the level of the junctions is a grid whose conductivity is higher than that of the wafer substrate and whose individual elements are disposed between adjacent ones of the junctions. Advantageously, respective ones of the P conductivity type regions are contained in individual mesas extending from the face of the wafer substrate so that each row of junctions is separated from an adjacent row ofjunc tions by a channel in the wafer substrate. In further keeping with the invention the conductive grid is formed by implanting ions into the floors of the channels between the rows of junctions so as to increase the conductivity of the wafer substrate below the channels in a grid-shapcd pattern.

Although it is conceivable that the target might have a P conductivity type substrate having an array of N conductivity type regions swept by a beam of positively charged particles, or by an electron beam at a voltage at which a target suffers a net loss of electrons due to secondary emission. it will be assumed in the following discussion that the target is swept by a charging electron beam, as will usually be the case, and that therefore the conductivity of the wafer substrate will be chosen to be N-type. in accordance with the present invention, and assuming an N conductivity type substrate, the conductive grid may be either of the same (N) conductivity type the substrate or it may have the opposite (P) conductivity type in which case provi sion may be made to maintain an operating bias on the grid relative to the scanning beam in order to further enhance the effect of the grid. Since the conductivity of the grid is greater than that of the surrounding substrate, it will be referred to herein as having either a P+ or N+ type conductivity. The same convention will also be used when referring to the diode forming regions (P+), since their conductivity is also greater than that of the wafers substrate (N) surrounding them.

Provision of the conductive inter-diode regions (either P+ or N+) between adjacent junctions alleviates the leakage current problem by taking the substrateinsulator interface out of the depletion region. As a result the generation-recombination centers along the substratednsulator interface are prevented from injecting spurious holes into the substrate and into adjacent diodes.

Blooming is reduced by the N+ inter-diode regions for two reasons: (1 Excess holes from a given junction diode tend to combine with excess electrons in the inter-diode conductive regions, thus being prevented from reaching and discharging adjacent diodes; (2) The inherent field which exists between the inter-diode region and the substrate thereunder is of a polarity which tends to oppose charge migration to neighboring diodes. If the inter-diode region is of the P+ conductiv ity type, connected to an external biasing circuit, blooming is reduced because of the ability of the P+ region to remove excess holes through the biasing circuit.

Finally the provision of the conductive regions between adjacent diodes also serves to alleviate the problem of inversion. If the conductive region has an N+ conductivity, it provides a negatively charged region between adjacent diodes which would require an increased target potential for its inversion than would be the case if only the normally doped N conductivity type substrate were disposed between the adjacent diodes. If a P+ conductivity type grid is used, inversion is not prevented thereby, but is indeed enhanced. However, when used in a mesa type junction diode target, the P+ conductivity type grid can still be useful, provided that the channel between adjacent diodes is made suffi ciently deep so as to separate the grid at the bottom of the channel from the P+ conductivity type regions at the tops of the mesas. This prevents the formation of a continuous inversion layer between adjacent diodes. since the electron beam which strikes the diode side of the target and which tends to cause inversion at the bottom of the channels does not strike the walls of the channels so that an inversion layer is not created thereon. An additional advantage of the externally biased P-ltype grid is that it provides a means for adjusting the sensitivity of the target, since, when reverse bi ased, the P+ grid competes with the reverse biased junction diodes for the light generated holes, and its effectiveness in so doing is determined by the magnitude of the grid bias as compared to the bias on the diodes.

Further advantages of the invention will become apparent from the following detailed description with reference to the attached drawings in which:

FIG. I is a cross-sectional schematic illustration of a vidicon camera tube incorporating features of the present invention;

HO 2 is a cross section through a conventional junction diode target illustrating the depletion region formed therein at different target potentials;

FIG. 3 is a cutaway perspective view of a mesa-type junction diode target made in accordance with the present invention and having an N+ conductivity type grid;

FIG. 4 is a cross-sectional view through a target similar to that illustrated in FIG. 3 but having a P+ conductivity type grid and also illustrating a reverse biasing circuitry for the grid;

FIG. 5 is a cross section through a mesa-tupe junction diode target illustrating the depletion region existing in the target in the absence of the conductive grid of the present invention;

FIG. 6 is a cross section through the same target as shown in FIG. 5 but illustrating the nature of the depletion regions with the N+ conductivity grid added.

FIGS. 7a-7g are successive cross-sectional views showing the target of FIG. 3 at successive points of its fabrication.

Referring now to the figures, a vidicon camera tube incorporating a junction diode target of the present invention is illustrated in FIG. 1. Principally it includes within a sealed glass envelope [3 a target near one end of the envelope next to a window 17 therein, and means 19 near the opposite end of the envelope for generating an electron beam 21 and for periodically scanning the diode-covered side 16 of the target therewith. The electron beam generating and scanning means 19 may be of conventional design which need not be described in detail and is illustrated as including an electron gun assembly 23 and beam deflection devices 24. The electron gun includes a cathode 25 from which the electron beam is generated and whose potential determines the potential of the electron beam. The body of the target 15 is maintained at a positive potential relative to the electron beam 21 by a biasing means 27, shown as a battery, connected between the cathode 25 and the target 15 through a load resistor 29, so that the diodes in the target are reverse biased and receive an electric charge from the electron beam which scans them.

Light from an image 31 is directed at the imagereceiving side 18 of the target 15 through the envelope window 17 by an optical system schematically indicated by the lens 33.

As photons from the image 31 strike the target side 18, electron-hole pairs are generated near the point of impact, and the holes of the pairs travel to the diode side 16 of the target, where they combine with the electric charge stored in the particular diode which they reach. In this manner the diode side of the target 15 loses its charge in a pattern corresponding to the image 31. Consequently, during the next scan of the electron beam 21, the respective diodes of the target receive an amount of charging current proportional to the amount of charge which they had lost. The resulting current fluctuation is detected in the biasing circuit at the point 35 as a voltage change and is used to produce a voltagevariable signal representative of the detected image.

The operation of the vidicon tube described thus far is essentially the same as with existing targets, such as that illustrated in FIG. 2, and reference may be made thereto for a fuller understanding of the phenomenon by which a light image is converted into a charge pattern in the junction diode type vidicon target. Referring to FIG. 2, the junction diode vidicon target 37 illustrated therein includes wafer substrate 39 having a scanned face 41 in which a large number of closely spaced. extremely small. P conductivity-type doped regions 43 have been formed. Covering the face 41 is an oxide layer 45 with openings therein, so as to expose each of the doped regions 43. Usually the entire scanned face 41, including both the doped regions 43 and the oxide layer 45, is covered by a resistive sea" 47 whose function is to prevent excessive charge from accumulating upon the oxide layer 45. The opposite face of the target 37 is usually doped more heavily than the substrate 39 so as to have a conductivity greater than, but of the same type as, the substrate. This is shown in FIG. 2 by the N+ layer 49. The purpose of the layer 49 is to produce a field gradient whose effect is to encourage the migration of holes toward the diode regions 43 when the target 37 receives light from the image. The substrate 39 of the conventional target 37 in FIG. 2 is shown to be connected to the resistor 29 as it would be if the target were used in the tube illustrated in FIG. 1.

Each of the P regions 43 forms a diode junction with the substrate 39 and, upon being scanned by the electron beam 21, accumulates an amount of charge determined by the target potential between the substrate 39 and the electron beam 21. At relatively low target potentials each of the P regions 43 is surrounded by an individual depletion region illustrated by the substrate between the regions 43 and the dashed lines 51 under those regions. As indicated previously, each of the depletion regions is characterized by a shortage of electrons. Moreover, essentially the entire target potential appears across the depletion regions. As the target potential is increased so does the volume of the substrate falling within the depletion regions. Ultimately the individual depletion regions merge so as to produce a continuous layer under the target surface 41 as illustrated by the portion of the substrate between the target surface 41 and the dashed line 53. It is the targets of the type illustrated in FIG. 2 which are are characterized by the three limitations of leakage current, blooming, and inversion discussed in the introductory remarks to the specification and reference to that portion of the specification in conjunction with FIG. 2 will be helpful in gaining further understanding of the phenomena there described.

The improved target 15 of the present invention is illustrated in detail in FIG. 3. It too is comprised principally of an N conductivity type semiconductor wafer substrate 54 having an array of P-type conductivity areas 56, each area forming a P-N diode with the underlying portion of the substrate. In its preferred embodiment illustrated in FIG. 3 the P conductivity type areas 56 are defined by mesas 5S ich extend from the face of the wafer substrate 54, each mesa having a P conductivity type layer 56 at itstap and a P-N junction 58 slightly above the face of the substrate. The mesas 55 are arranged in a plurality of rows and columns separated by channels 57, with an insulating layer 59 covering the channels but leaving the tops of the mesas 55 exposed. A resistive sea 61 covers both the insulating layer 59 and the tops of the mesas 55. An N+ conductivity layer 63, similar to the layer 49 in FIG. 2, is formed in the opposite face of the substrate 54. Indeed respective ones of the portions 56, 59 and 61 of FIG. 3 correspond to. and perform the same function as. the portions 43, 45 and 47 in the conventional junction diode target shown in FIG. 2.

As described thus far, the target illustrated in FIG. 3 would have the same inherent limitations as does the target of FIG. 2. In accordance with the present invention. however. there is additionally provided in the target of FIG. 3 a grid 65 formed in the substrate 54 immediately below the insulating layer 59, the grid being formed by portions of the substrate 54 doped to have a greater conductivity than the remaining portions of the substrate. In the embodiment illustrated in FIG. 3, the conductive grid 65 has the same conductivity type as does the substrate 54 and is characterized by the fact that the width of its individual inter-diode isolator portions is slightly smaller than the width of the channels 57 so as to provide a finite spacing between the elements of the grid and the P+ conductivity type regions 56 of the mesas S5.

The beneficial effect of the conductive grid of the present invention may be better understood by refer ring to FIGS. 5 and 6 which respectively illustrate the depletion region which can exist in a mesa-type diode such as that illustrated in FIG. 3 without and with a conductive grid. Thus as shown in FIG. 5, at higher target potentials there exists a continuous depletion layer above the dashed line 67, extending both under the P+ mesas 55 and under the channels 57 between them. Consequently, the silicon-oxide interfaces 69 between the substrate 54 and the channel insulating oxide 59 fall within the depletion region and therefore provide a relatively large number of generation-recombination centers within that region. As explained previously, this results in a relatively large leakage current due to the generation of holes at the centers within the depletion region which have the same effect when they reach one of the P+ mesas 55 as would a hole produced as a result of light-striking the target opposite the mesa. The mesa target illustrated in FIG. 3 is also subject to the formation of an inversion layer in the substrate between adjacent diodes caused by electrons landing thereon from the scanning beam. Similarly the mesa target of FIG. 3 is subject to blooming, whereby excess holes which cannot be absorbed by a given diode region spread laterally to adjacent regions, discharging them.

Referring now to FIG. 6, the manner in which all three of these problems are alleviated by the conductive grid of the present invention becomes apparent. Instead of the continuous depletion layer represented by the dashed line 67 in FIG. 5, the N+ conductivity regions 65 between adjacent P+ mesa regions 55 prevent the depletion layer from forming under the channels 57 and confine them to individual regions 71 under the respective P+ regions 55. Consequently, the silicon-oxide interfaces 69 are no longer within the depletion regions and hence they no longer contribute effective generation-recombination centers whereby undesired holes might be generated. This, therefore, diminishes the leakage problem. Similarly, as explained previously, the excess electrons in the N+ regions 65 under the channel-insulating oxide portions 59 resist the formation of inversion layers under those oxide portions. And. finally, blooming is significantly reduced because the voltage gradient resulting from the N+ regions 65 provides an obstacle to the lateral migration of holes between adjacent diodes. Furthermore, holes which migrate from a flooded" diode to an adjacent diode tend to combine with the excess electrons in the interdiode grid regions 65, thus further reducing their probability of spreading.

It should be noted that. while the conductive grid of the present invention lends itself particularly to a mesatype target construction. many of the same principles by which it improves target operation would also apply if it were incorporated in a conventional type of junction diode target such as that illustrated in FIG. 2. It should also be noted that the advantages which are derived from the present invention are due to the presence of a relatively highly conductive interdiode isolator region between adjacent diodes in the target. The fact that the individual regions form a single grid is derived simply from the fact that the diodes are usually fabricated in an ordered array of columns and rows so that it is convenient to integrate the inter-diode isolators into a single grid.

An alternative embodiment of the invention in which the inter-diode isolators have a conductivity type opposite to that of the substrate is illustrated in FIG. 4. The modified embodiment of FIG. 4 is shown in cross section rather than in perspective as in FIG. 3 and differs from the embodiment of FIG. 3 only in the conductivity type of its inter-diode isolators and in that additional biasing means are optionally provided therefor. All other elements illustrated in the FIG. 4 modified embodiment correspond to the elements shown in FIG. 3 and are identified by the same reference numerals but with an apostrophe added. The distinguishing element of the modified embodiment of FIG. 4 is the grid of inter diode isolators 73 having a P+ conductivity type and disposed in the substrate 54' immediately under the channel-insulating portions 59. Biasing means 79, shown as a variable voltage battery, is preferably connected between the cathode used for generating the electron beam 21 and the inter-diode isolators 73. A biasing battery 77 and a load resistor corresponding to the elements 27 and 29 in FIG. I are connected between the cathode and the substrate 54' to impose a reverse bias on the diode junctions 58'. Preferably the biasing means 79 is adjusted to impose a positive potential on the interdiode isolators 73 relative to the electron beam generating cathode, which potential is less than that imposed on the substrate 54'. The presence of the P+ conductivity type inter-diode isolators 73 also has the effect of removing the silicon-oxide interfaces 69' from the depletion regions created by the P+ diode regions 56' and hence reduces leakage current in a manner analogous to that of the N+ conductivity type interdiode isolators 65 of FIG. 3. Blooming is prevented by the ability of the biasing circuit to remove holes which through lateral migration have reached the isolating regions 73. And the arrangement of FIG. 4 has the additional advantage of permitting the sensitivity of the target to be varied by adjustment of the grid biasing potential imposed by the battery 79. Thus the greater the potential imposed upon the inter-diode isolators 73 by the battery 79, the larger the number of holes that are diverted by those isolators from reaching the diode regions 56', since the reverse biased isolating regions 73 compete with the reverse biased diode regions 56' for holes generated by light striking the back surface of the target. Indeed by increasing the potential imposed by the battery 79 to a higher potential than that imposed upon the diode regions 56' by the battery 77, the target can be turned off" since effectively all of the light-generated holes will be diverted to the inter-diode isolators 73 and will not reach the diode regions 56.

A preferred manner of fabricating a mesa-type junc tion diode target incorporating features of the present invention as shown in FIG. 3 is based on a process dis closed and claimed in patent application Ser. No.

168,7 l3 by Aubuchon, Dill, and Bower entitled Self- Registered Doped Layer For Preventing Field lnversion ln MlS Circuits" filed Aug. 3, 1971. now U.S. Pat. No. 3,748,187. and assigned to the assignee of the pres ent invention. As applied to the present invention and as illustrated in FIGS. 7a-7g, the initial step in the process is to deposit a layer of silicon nitride 81 on a silicon wafer substrate 54 (FIG. 7a). An array of channels 83 is then etched in the silicon nitride layer 81, through openings in a conventional photoresistive mask (not shown). Next, using the silicon nitride layer 81 as a mask, channels 85 are excavated from the wafer substrate 54 so as to form the mesa 55 therebetween.

A preferred method for excavating the channels 85 is to expose the substrate 54 through the openings 83 in the silicon nitride mask 81 to an etchant for a sufficient period of time to cause the etchant to slightly undercut the silicon nitride mask as shown in FIG. 7c. After the formation of the channels 85, the inter-diode isolator elements 65, which together form the grid, are created in the bottom portions of the excavated channels 85 by further doping the substrate 54 (FIG. 7d). Preferably the inter-diode elements of the grid 65 are made narrower than the channels above them and this is conveniently achieved by implanting conductivitydetermining ions in the wafer 54, using the layer 81 as a mask.

The technique of increasing the conductivity ofa desired portion of a semiconducting substrate, by bombarding it with ions commonly called ion implantation", is well-known and particularly suited for the doping of the substrate below the excavated channels 85 either to a P+ or an N+ conductivity since ions travel in a straight line and the doped areas 65 would substantially correspond to the openings 83 in the mask 81 and would be narrower than the excavated channels 85.

The conductivity type of the grid 65 may be either N-+- or P+. For a further discussion of ion implantation as a method for selective doping of a semiconductive substrate, reference may be made to US. Pat. No. 3.5 l4,844 issued to Bower and Shifrin and assigned to the assignee of the present invention.

With the conductive grid 65 formed. the next step is to form the channel insulating portions 59, preferably by growing a layer of thermal oxide on the exposed channel surfaces of the wafer substrate 54 (FIG. 7e). By performing this step the wafer is exposed to an oxidizing atmosphere such as steam at an elevated temperature. whereby the surfaces of the channels 85 become oxidized and acquire a layer of silicon oxide thereon, while the tops of the mesas 55 are prevented from acquiring such a layer by the remaining portions of the silicon nitride mask 81. The mask 81 is then stripped (by hot phosphoric acid if the mask is silicon nitride) so as to expose the tops of the mesas 55 (FIG. 7]) which are then doped. preferably by a conventional diffusion doping step, to have a P+ conductivity so as to form the diode regions in the mesas 55. To improve the eventual performance of the target. the wafer 54 may be annealed and otherwise treated at this point as by the formation of a resistive sea 61. for example. after which the wafer 54 is thinned. typically by etching, and finally doped on its backside to acquire an N+ type conductivity as shown in H6. 7g. The last doping step may again be by a conventional diffusion doping technique.

Typical dimensions for a target made by the process illustrated in FIG. 7u-7g would include a wafer whose initial thickness is about lSO microns and in which mesas l0 microns wide are formed with channels approximately 5 microns wide and 3 microns deep between them. The ion implanted grid regions under the channels are approximately 1 micron deep and about 3 microns wide. After the thinning step of FIG. 7g the ultimate thickness of the target is of the order of 20 microns.

There has thus been shown and described an improved junction diode target and a method of fabricating a preferred embodiment thereof. The resulting target is no more difficult to make than existing types. yet they offer the potential of better performance through reduced blooming, reduced leakage current and higher resistance to inversion. Consequently, the junction diode target of the present invention permits the production of a better silicon vidicon camera tube by virtue of the fact that the target is better able to respond to high intensity point light sources in a low level light background because of the greatly reduced tendency of the target of the present invention to sustain blooming under such light conditions. Moreover. in addition to its improved performance, the junction diode target of the present invention has the additional feature of adjustable sensitivity when implemented with a reverse biased grid whose conductivity type is opposite that of the target substrate.

What is claimed is:

1. A vidicon camera tube comprising:

A. an evacuated envelope having a radiation transmissive window;

B. a charge storing target facing said window and including:

1. an N conductivity type silicon substrate disk having an array of P+ conductivity mesas extending from one of its two major faces, each said mesa forming a P-N junction with the underlying portion of said substrate;

2. a silicon dioxide layer covering the wall of said mesas and the surface of said substrate between said mesas;

3. a P+ conductivity type grid formed of said substrate immediately below that portion of the substrate surface that is covered by said silicon dioxide layer entirely below the level of said P-N junctions, and spaced from said array of mesas; and

4. an N+ conductivity type layer formed of the other of the two major faces of said substrate. said other substrate face being next to said window; and

C. means facing said array of mesas for generating a beam of electrons and means for scanning said array of mesas therewith.

2. A vidicon camera tube comprising:

A. an evacuated envelope having a radiation transmissive window;

B. a charge storing target having:

1. an N conductivity type semiconductor substrate disk having an array of mesas extending from one of its major faces and forming a plurality of channels therewith. each said mesa having a P conductivity type layer at its top and a P-N junction above its base;

2. an insulating layer covering said channels; and

3. a P+ conductivity type grid formed of said substrate disk immediately below said channels. en-

tirely below the level of said P-N junctions, and

confined within the width thereof so as to space them from said array of mesas, said grid having a greater conductivity than the remaining portions of said substrate; and

C. means facing said array of mesas for generating a beam of electrons and means for scanning said 

1. AN N CONDUCTIVITY TYPE SILICON SUBSTRATE DISK HAVING AN ARRAY OF P+ CONDUCTIVITY MESAS EXTENDING FROM ONE OF ITS TWO MAJOR FACES, EACH SAID MESA FORMING A P-N JUNCTION WITH THE UNDERLYING PORTION OF SAID SUBSTRATE;
 1. A VIDICON CAMERA TUBE COMPRISING: A. AN EVACUATED ENVELOPE HAVING A RADIATION TRANSMISSIVE WINDOW; B. A CHARGE STORING TARGET FACING SAID WINDOW AND INCLUDING:
 2. A SILICON DIOXIDE LAYER COVERING THE WALL OF SAID MESAS AND THE SURFACE OF SAID SUBSTRATE BETWEEN SAID MESAS;
 2. an insulating layer covering said channels; and
 2. A vidicon camerA tube comprising: A. an evacuated envelope having a radiation transmissive window; B. a charge storing target having:
 2. a silicon dioxide layer covering the wall of said mesas and the surface of said substrate between said mesas;
 3. a P+ conductivity type grid formed of said substrate immediately below that portion of the substrate surface that is covered by said silicon dioxide layer entirely below the level of said P-N junctions, and spaced from said array of mesas; and
 3. A P+ CONDUCTIVITY TYPE GRID FORMED OF SAID SUBSTRATE IMMEDIATELY BELOW THAT PORTION OF THE SUBSTRATE SURFACE THAT IS COVERED BY SAID SILICON DIOXIDE LAYER ENTIRELY BELOW THE LEVEL OF SAID P-N JUNCTIONS, AND SPACED FROM SAID ARRAY OF MESAS; AND
 3. The combination of claim 2 wherein means are provided for maintaining said grid at a positive potential relative to said P+ conductivity mesas during said scanning.
 3. a P+ conductivity type grid formed of said substrate disk immediately below said channels, entirely below the level of said P-N junctions, and confined within the width thereof so as to space them from said array of mesas, said grid having a greater conductivity than the remaining portions of said substrate; and C. means facing said array of mesas for generating a beam of electrons and means for scanning said array of mesas therewith.
 4. an N+ conductivity type layer formed of the other of the two major faces of said substrate, said other substrate face being next to said window; and C. means facing said array of mesas for generating a beam of electrons and means for scanning said array of mesas therewith.
 4. AN N+ CONDUCTIVITY TYPE LAYER FORMED OF THE OTHER OF THE TWO MAJOR FACES OF SAID SUBSTRATE, SAID OTHER SUBSTRATE FACE BEING NEXT TO SAID WINDOW; AND C. MEANS FACING SAID ARRAY OF MESAS FOR GENERATING A BEAM OF ELECTRONS AND MEANS FOR SCANNING SAID ARRAY OF MESAS THEREWITH. 